This invention relates to an improved semiconductor integrated circuit reducing the adverse influences of minority carriers.
Recently, semiconductor technology for manufacturing integrated circuits has advanced in that memory size of one-chip memory has been substantially enlarged. FIG. 1 illustrates a conventional memory cell circuit of N-type channel MOS static random access memory (RAM). This memory is composed of a flip-flop circuit constructed of a pair of inverter circuits 5 and 6 and a pair of transmitting transistors 9 and 10 connected to data lines 7 and 8 respectively. Inverter circuits 5 and 6 have driving transistors 1 and 2 and load resistors 3 and 4 respectively. Load resistors 3 and 4 are preferably made by high resistance polycrystalline silicon. This type RAM is called a four transistor and two resistor RAM. The values of load resistors 3 and 4 are produced by ion implantation in which the impurity is injected into the undoped polycrystalline silicon layer. The value of resistors 3 and 4 has a minus gradient characteristic with change of temperature so that resistance becomes low at elevated temperatures. The increasing supply current of the load resistor compensates the leakage current of the PN junction.
Load resistors 3 and 4 are ordinarily in the range several M.OMEGA. to several hundred M.OMEGA. at high temperatures. However, the value of load resistors 3 and 4 extremely increases into the G.OMEGA. (10.sup.3 M.OMEGA.) range at low temperatures. When the RAM is operated at low temperature, the leakage current of the PN junction decreases at a rate much greater than the rate of resistance increase. For example, when temperature goes down from 100.degree. C. to 25.degree. C., the leakage current decreases by 3 to 4 orders of magnitude, but the value of the resistors increases no more than two. Consequently, load resistors 3 and 4 have sufficiently performed to retain the data.
However, when the value of load resistors 3 and 4 becomes extremely high, these resistors are apt to be affected by the minority carriers produced from peripheral circuits other than memory. In addition, the lower the temperature, the longer the lifetime of the minority carriers so that their influence on memory is stronger. FIG. 2 illustrates the consequence of the minority carriers of a RAM composed of N-type channel transistors. Transistor T (shown by dotted line) is a element of peripheral circuits, for example, an input circuit and a self-substrate biasing circuit, etc. Minority carriers (electrons) 11 generated at N+ region 12 inject into P-type substrate 13 and reach another N+-type region 14 which is a part of the memory stored "1" level. Minority carriers 11 recombine with holes in N+-type region 14, thereby the "1" level loses a portion of carriers. In the worst case, the "1" level is broken by the minority carriers. This phenomenon is apt to result at lower temperatures with high values of resistors 3 and 4 (shown in FIG. 1). Therefore, it is desirable to lower the value of resistors 3 and 4 to prevent the outbreak of this phenomenon. However, if the value of the resistors of all memory is lowered, the electric power consumption of all of the RAM grows.
FIG. 3 illustrates another memory which consists of data storage capacity C.sub.1, data transmitting MOS transistor Q.sub.1, word line W, data line D and parasitic capacity C.sub.ST associated with data line D. In this type memory, writing of the data is performed by transmitting the electrical potential level at data line D to capacity C.sub.1, through transistor Q.sub.1 selected by word line W. Reading of the data is performed by sensing the electric potential level V.sub.1 as the stored data in capacity C.sub.1 through transistor Q.sub.1 selected by word line W.
However, the minority carriers can destroy the stored data of above-mentioned memory as shown in the FIG. 3. FIG. 4 illustrates the influence of the minority carriers, and similar elements in FIG. 3 are assigned the same reference numbers as above.
Transistor Q.sub.1 consists of a gate electrode 41 made of poly-crystalline silicon and two N+-type regions 42 and 43. Capacity C.sub.1 is constructed as the sum of capacities C.sub.11 and C.sub.12. Capacity C.sub.12 is formed between capacitor electrode 44 and reverse layer 45 produced on the surface of P-type substrate 46 at applying bias V.sub.cc. Capacity C.sub.11 is a PN junction capacity. Minority carriers are electrons 47 and are generated from N+-type region 48 of a peripheral circuit. If the minority carriers reach the memory cell, these carriers jump into the data storage mode of the memory and recombine with holes. The "1" level drops corresponding to the quantity of the minority carriers. When the minority carriers are too many, the "1" level is lost and the data destroyed. This phenomenon becomes more common at the lower temperatures in which lifetime and mobility of the minority carriers is increased.
A guard ring structure is known to improve the above-mentioned fault, for example, in U.S. Pat. No. 4,163,245. Namely, N+-type guard ring region 49 shown in FIG. 4 is provided around the memory and is connected to an electric source. Such region cannot perfectly guard the memory cells from minority carriers which pass through the deeper portion of substrate 46. A radical counter-measure is to enlarge the storage mode capacity C.sub.1 of the memory. However, this structure hinders increasing storage capacity.